CA-CSTP: a new BIST architecture for sequential circuits
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante · 2002
Circular Self-Test Path (CSTP) is an attractive technique for implementing BIST in sequential circuits; unfortunately, there are cases in which the fault coverage it attains is unacceptably low. This paper proposes a new architecture, named CA-CSTP, which overcomes these limitations and always reaches a high fault coverage by exploiting a slightly more complex chain cell based on a Cellular Automata architecture. Experimental results show the effectiveness of our proposal.