Extending VHDL for state based specifications
Johannes Helbig · 2002
Statecharts can complement VHDL, in particular for system level design. We present what would be needed to extend VHDL by state based specification, sharing its syntax and the fundamental notion of time. The resulting integration is very tight, allowing, by comparison to existing approaches, more precise control for synthesis, incorporation of library components, multiple statechart instantiations and smooth paradigm switches. The language is being developed and implemented in the ESPRIT project FORMAT, and has been successfully employed for formal verification against timing diagram specifications.