A programmable solution for standard video compression
Jan Fandrianto, T. Williams · 2003
The emergence of the CCITT H.261, MPEG, and IPEG video compression standards has created the need for hardware capable of executing all of these standards. It is pointed out that the Integrated Information Technology (IIT) Vision Processor (VP) and Vision Controller (VC) chips provide a flexible, programmable solution capable of executing H.261, MPEG and JPEG. The VP is the first programmable video signal processor optimized for algorithms based on the discrete cosine transform (DCT). The VC is a companion chip which includes a RISC (reduced instruction set computer) microcontroller to manage the system data flow. These two chips with memory can act as an H.261 QCIF codec, and H.261 FCIF encoder or decoder, a real-time FCIF JPEG encoder or decoder, and an SIF MPEG decoder.>