Architecture of a ladder solving processor (LSP) for programmable controllers
W.H. Kwon, J. Kim, Joonyeop Park · 2002
The authors propose a dedicated architecture of a ladder solving processor (LSP) for programmable controllers. A mathematical representation of the ladder language is suggested and algorithms for solving this ladder language are presented using abstract notations. The performance of the proposed architecture was demonstrated by an experimental prototype of the LSP. Computer simulations showed that, under reasonable assumptions, the proposed LSP can process the pure logic instruction group at 45.5 MIPS using eight cells. In case of a ladder program, a quarter of which is the box instruction group, the LSP can process at the rate of 0.27 ms/Kstep using a single-cell architecture, and at the rate of 0.18 ms/Kstep using four cells. This speed is much faster than that of the existing programmable controllers.>