A low power 1D-DCT processor for MPEG-targeted real-time applications
Min Jiang, Yuan Luo, Yiling Fu, Bing Yang, Baoying Zhao, Xin’an Wang, Shimin Sheng, Tianyi Zhang · 2005
A 1D-DCT processor with parallel pipelined VLSI architecture is designed for MPEG visual and audio applications. The processor is based on distributed arithmetic to obtain low power and high computation efficiency. The simulation with EDA software shows that the pipelined parallel architecture can reach an efficient compromise between hardware cost and computing speed for real-time MPEG-related applications.