ILP-based modulo scheduling for high-level synthesis
Julian Oppermann, Andreas Koch, Melanie Reuter-Oppermann, Oliver Sinnen · 2016
In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling.