New design methodologies for low complexity fir filters and reconfigurable constant multipliers
Jiajia Chen · 2010
Multipliers, being the area and power hungry units, are deciding factors to the overall area, speed, and power consumption of digital circuits. To meet the stringent design requirements, multiplications have been avoided, reduced or replaced if possible by powerful design methodologies in high-level synthesis for many compute intensive digital signal processing problems. Multiple Constant Multiplication (MCM) and Reconfigurable Constant Multiplier (RCM) problems are two typical problems that have attracted a lot of attention in recent years. In this thesis, the first part presents a new paradigm of design methodology to reduce the complexity of MCM block of finite impulse response (FIR) digital filters. Motivated by the advantages of reconfigurable architectures, this thesis also presents a new high level design methodology for RCM block. This new technique leads to two new architectures for the implementation of circular convolution. Last but not least, an efficient switching power estimation method for the MCM block of FIR filter is proposed in view of the inefficiency of using gatelevel and circuit-level techniques for its power estimation.