Systemverilog for Design and Verification Using Uvm: From Rtl to Synthesis
Mark A. Azadpour · 2016
This book is an A-Z guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC). To complete this books package as a practical guide, readers are introduced to the fundamentals of static timing analysis.