FPGA Implementation for Modified RCM-RW on Digital Images
Hirak Kumar Maity, Santi P. Maity · Journal of Circuits Systems and Computers · 2016
Reversible contrast mapping (RCM) and its various modified forms are used extensively in reversible watermarking (RW) on digital images to embed secret information. Sometimes RW demands real-time implementation that can be made by hardware realization and RCM-based RW becomes appealing due to its integer transform nature followed by least significant bit (LSB) substitution for embedding. This motivates us to propose RCM-RW on digital images with two objectives: modification on the existing RCM algorithm to increase embedding rate with low visual distortion. Later on, prototype design through field-programmable gate array (FPGA) is developed for a (256 × 256), 8-bit gray scale image using (32 × 32) image block and pipeline architecture. For a cover image of size (256 × 256), the proposed architecture requires 8,971 slices, 8,246 slice flip-flops, 9,706 numbers of four-input LUTs and 2 FIFO 16/RAMB for watermark embedding purpose. Proposed architecture consumes a power of 636[Formula: see text]mW and offers a data rate of 1.0493[Formula: see text]Mbps at an operating frequency as high as 95.3[Formula: see text]MHz.