High-speed and Huge-capacity Data Cache System Based on FPGA
Fei Gao, Wenge Chang, Xiang‐Yang Li · 2016
Aiming at the high-speed and huge-capacity data cache and transmission caused by real-time signal processor for high-resolution SAR, this paper presents a design for the high-speed and huge-capacity data acquisition system based on DDR3 SDRAM and RapidIO.Data cache is realized by MIG3.92 IP core in Xilinx Virtex_6 series FPGA.Data Transmission is realized by RapidIO IP core and GTX.The testing results show that the maximum write rate of DDR3 memory is 3120MB/s and the transmission rate of RapidIO interface is 1800 MB/s.