Parallel implementation of arbitrary-sized Discrete Fourier Transform on FPGA
Lin Shu, Jie Hao, Chengcheng Li, Hui Feng, Donglin Wang · 2016
Discrete Fourier Transform(DFT) is one of the frequently used kernels in a variety of signal processing applications. Most previous state-of-the-art work has focused on the transform size of a power of 2. And many implementations of non-power-of-two sized DFT is customized for a specific application. In this paper, a parallel-processing architecture based on Field-Programmable Gate Array (FPGA) for arbitrary-sized DFT is proposed. In particular, it is attractive to use to compute DFT with arbitrary prime size. A memory efficient data mapping scheme for twiddle factors is proposed, which reduces the storage size of twiddle factors from n2to kn(k is a constant). We implement a design with 196 processing elements, which is available for any transform size n from 14 to 1024. For a transform size of 59, the throughput in this design can reach to 737.5 Msps. The design can be easily extended to be one with more processing elements if the hardware has enough resources. And we have built a code generator to automatically generate designs with different numbers of processing elements.