Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs
Jori Winderickx, Joan Daemen, Nele Mentens · 2016
We explore the possibility of using shift register lookup tables (SRLs) for the implementation of Keccak on Xilinx FPGAs. The approach originates from the observation that the ρ step in combination with the state storage can be implemented as a collection of shift registers. This way, we achieve a slice-wise implementation using 25 shift registers of various lengths, resulting in 75 32-bit and 6 16-bit SRL primitives on a Virtex-5. This approach, however, does not comply efficiently with the common interface of Keccak. We therefore propose to utilize a modified interface in order to avoid the redundant storage of the state. This modified version of Keccak, with equivalent cryptographic strength, can be implemented without Block RAM, outperforming all previously proposed implementations in terms of the number of slices. Furthermore it outperforms several other lightweight slice-wise implementations in terms of throughput.