Embedding a Low Power Test Set for Deterministic BIST using a Gray Counter
Subrata Kundu, Santanu Chattopadhyay · 2011
We propose a new technique to generate a fully specified pre-computed low power test set in a deterministic BIST using simple gray counters within reasonable clock cycles. In our approach, only a small part of the circuit under test (CUT) is active, the rest of the CUT is fed with low leakage input patterns. Even the active part is fed by a gray counter which make the overall power consumption extremely low. The approach requires moderate number of reseeding and nominal hardware overload over pseudo random BIST using LFSR or CA. Moreover, instead of storing in the memory, the seed patterns can also be fed through a low cost, slow tester which allows us to efficiently combine a BIST with external testing using slower tester