An implementation method of the box filter on FPGA
Sichao Wang, Tsutomu Maruyama · 2016
The box filter is widely used in image processing. Its computational complexity is low, and many other filters can be realized by using different size box filters. The implementation method of the box filter that is widely used in the software programs requires an array to store data, the size of which is filter size × image width. This array often limits the feasibility of the box filter on FPGA, because its size is proportional to the image width. In this paper, we show an implementation method of the box filter that requires less memory. Two types of wide-width but shallow memory are required in this method, but these memory can be efficiently realized on FPGA using distributed RAMs and block RAMs. In this method, the image is scanned in zigzag. The performance is decreased because of the necessity to overlap the zigzag scan, but it is fast enough for practical use. This zigzag scan enable to reduce the memory size to store data, but extra line buffers are required. Our approach is specially effective for applications that calculate cross-correlations for finding the best matching, because the overhead caused by the extra line buffers becomes relatively small in these applications. We show the effectiveness of our method using a stereo vision program based on the cost aggregation with guided filter.