A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS
Sanu K. Mathew, Sudhir K. Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Greg Chen, Ram Kumar Krishnamurthy, Vivek K. De · 2016
A 1024-bit delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential clock delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.