An FPGA-based reconfigurable DDC algorithm
Bartłomiej Juszczyk, Grzegorz H. Kasprowicz · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2016
This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.