IEEE 802.3 100Gbps Ethernet PCS IP design challenges and solutions
Udara De Silva, Anusha Lokumarambage, Hasantha Malavipathirana, Chathuranga Mohottala, Subramaniam Thayaparan · 2016
This paper identifies the challenges involved in designing the 100 Gigabit per second (Gbps) Ethernet Physical Coding Sublayer (PCS) Semiconductor Intellectual property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics, implementation challenges and verification challenges. Furthermore, our solutions to identified challenges are presented in the paper.