Boosting convergence of timing closure using feature selection in a Learning-driven approach
Que Yanghua, Harnhua Ng, Nachiket Kapre · 2016
Machine Learning approaches for automated selection of FPGA CAD tool parameters have been demonstrated to be useful for timing closure of FPGA designs [3], [4]. This is achieved by running the CAD tool multiple times with small variations in the the CAD parameter values. The timing slack from each run is recorded into a database along with all input parameter selections to help train a classifier. By progressively running more instances of the tool, we can help drive the CAD tool towards timing convergence. However, a naïve approach that uses simplistic off-the-shelf learning libraries and uses all features (CAD parameters) is inappropriate. This can often miss opportunities inherent in specific design properties and nuances of the FPGA device family and tool versions while possibly overfitting the models and trapping the system into a local minima. In this paper, we show how to combine design-specific feature selection with a set of classification approaches that are configured to improve model quality and reduce the number of iterations required to deliver timing closure. We show how to systematically tailor the correct subset of features for each design to deliver robust results. Using design-specific feature selection, we prune the set of CAD parameters used for constructing the classifier model down from ≈80 to ≈8-22 features. We show improved AUC scores (Area under ROC curve) as high as 0.83 which represents an improvement over the baseline InTime scores of 0.74 earlier. We use a set of large industrial designs to show these results and lower the number of CAD iterations required for convergence by 3× (mean) using our proposed approach.