Reconfigurable circuit for implementation of family of 4-phase latch protocols
Jotham Vaddaboina Manoranjan, Kenneth S. Stevens · 2016
This paper presents a novel reconfigurable circuit capable of implementing the entire family of 4-phase latch protocols. The architecture utilizes look-up-table based reconfigurable logic structures and fixed signal paths. The implemented circuit creates a fabric to realize a variety of high speed and low power controllers for asynchronous circuits on FPGAs. The circuit is implemented on the IBM Artisan 65nm node and its performance is compared with implementations on a Xilinx Virtex-5 chip that is manufactured on a similar node. A 4× improvement in speed and 3.3× improvement in energy per cycle is achieved.