Compiler Transformations Meet CPU Clock Modulation and Power Capping
Wei Wang, Allan Porterfield, John Cavazos, Sridutt Bhalachandra · 2016
The HPC community is striving to achieve exascale computing within a power cap of 20 Megawatts. This paper studies the impact of power capped environments on compiler transformed programs. The impact of CPU clock modulation (a mechanism for reducing CPU frequency) on program variants of several Polybench benchmarks is studied. Our evaluation shows at least one scenario where a compiler transformed program is sped up by 16% under a power cap. Further, CPU clock modulation is seen to impact program variants differently depending on their underlying memory characteristics.