Remote FPGA Laboratory for Testing VHDL Implementations of Digital FIR Filters
Martin Petrvalský, Oto Petura, Miloš Drutarovský · Acta Electrotechnica et Informatica · 2015
In this paper, we develop a new remotely testable setup based on Altera Cyclone III field-programmable gate array.The setup is part of the European project EDIV I D E in which our department participates.The setup is prepared for an educational purposes in the field of the reconfigurable devices.The setup uses Nios II soft core processor with reconfigurable coprocessor for the digital filtration.The design of the coprocessor is provided in VHDL which can by modified by the end user.The Nios processor programmed in C language ensures an interface between the coprocessor and EDIV I D E project servers.The complete setup uses a Nios II Cyclone III embedded evaluation kit board with additional debug and monitoring interfaces for EDIV I D E project infrastructure.Besides the VHDL design and C implementation, we created a web interface for the remote testing and debugging of the end user designs.