Accelerated processing delay optimization in hierarchical networks using low cost hardware
Marian Ulbricht, Jens Wagner · 2016
Delay optimization is a today's topic. Delay is an important quality of service (QoS) parameter. In this paper, we present a technique that uses IP-addresses to encode the way a packet passes through the network without using a lookup table as well as a hardware accelerator to use this encoded information. Using this method, the time a packet that is delayed in the router is decreased dramatically, and the time to calculate the routing information is predictable. We show in simulation that this lookup is possible in about 5, 6 ns. The worst-case execution time (WCET) for routing information calculation is easy to estimate and is constant for a given path through the network and a given router. The new router design will save money and power compared to common designs.