Effective generation of functional models for logic simulation
Changho Han · 1991
This dissertation presents an automatic program synthesis system which automatically generates models for digital logic simulators. The generated models are C language subroutines to be used as element routines. Models can be generated from either behavioral or structural domain descriptions. Behavioral models are generated from Boolean equations, truth tables, or HDL descriptions. For structural models, schematic diagrams or HDL descriptions are used. Model verification is accomplished by simulation. Generated models are used as element routines for a parallel fault simulator, PARSIM. The system provides an efficient method for model development. Results show that the system can significantly reduce the model development cycle time. This is of major importance since new models are continually needed for new designs, throughout the lifetime of simulators.