IA-64 Code Generation
Vikram S. Rao · NCSU Libraries Repository (North Carolina State University Libraries) · 2000
Rao, Vikram. IA-64 code generation. (Under the direction of Dr. Tom This work presents an approach to code generation for a new 64-bit Explicitly Parallel Instruction Computing (EPIC) architecture from Intel, called IA-64. The major contribution of this work is the design of a machine independent optimizer, munger, that transforms code generated originally for a Very Long Instruction Word (VLIW) processor, called Tinker, to one that can run on the IA-64 architecture. The munger does this transformation by reading in a set of rules that specify a mapping from Tinker specific code to IA-64 specific code. The aim is to do this transformation outside the compiler back-end, thereby being able to take advantage of any optimizations that the back-end might perform on the code. This would also preclude rewriting the existing back-end significantly, to support the new architecture. The primary motivation for this approach was the fairly large similarity between the Tinker, and the IA-64 architectures. Besides, Tinker is an experimental VLIW architecture that supports a number of features to exploit instruction level parallelism (ILP) and can be easily extended to support new features. This makes the back-end for Tinker an ideal compiler to retarget for the IA-64 architecture, since it already performs most ILP optimizations that are supported on the IA-64.