An architecture for low-cost concurrent detection using continuous signature monitoring
KENT D. WILKEN · 1990
Concurrent error detection is becoming a necessity because errors caused by transient hardware faults are more likely as device size decreases, and as computers are subjected to noisier environments. Errors caused by deliberate faults, e.g., computer viruses, are also increasing as computer use and computer communication grows. This dissertation presents an architecture for low-cost concurrent detection of program execution errors caused by a broad range of sources, including transient hardware faults and computer viruses. The new approach, continuous signature monitoring (CSM), uses a simple hardware monitor and signatures that the compiler embeds into a program. CSM is shown to provide significant hardware-error detection coverage at a cost that is a small percentage of the cost of duplication, the traditional approach to concurrent error detection. CSM makes major advances beyond previous signature-monitoring techniques, including order of magnitude improvements in performance overhead, memory overhead, error detection latency, undetected control-flow errors, and signature-compiler performance. The short detection latency allows low-cost transient fault tolerance by using the processor's pipeline as a recovery buffer. A new efficient-approach to program encryption is proposed that is based on CSM. This approach further reduces signature overhead for detecting hardware faults, shortens detection latency, and allows significant resistance to computer virus attacks. The results from this research include new techniques, new analytical methods, new theory, and new experimental results. The MIPS RISC is used as an example architecture at several places in this dissertation to illustrate the minor modifications that are made to a conventional computer architecture to accommodate CSM.