Automatic circuit redesign for delay fault testability using constrained quadratic 0-1 programming
M.L. Bushnell, Izaz Shaik · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1994
We discuss three methods of automatically redesigning Very Large Scale Integrated circuits so that they can test themselves for excessive delay. A delay fault occurs when a circuit signal arrives too late as it propagates through the circuit. A hazard is the occurrence of multiple circuit signal transitions in a very short time interval. For delay fault testing to be accurate, we must eliminate hazards in the circuit by adding hardware. Our three methods for determining where to place this additional hardware are: (1) Good machine simulation using a higher-order Boolean algebra, (2) A graph algorithm to bound the enumeration of paths and find points where hazards appear, and (3) Quadratic 0-1 Programming to balance all cycles in the circuit graph. We discuss the mathematics of these three methods, present results, and discuss the inadequacies of each method. We conclude by proposing a greedy algorithm that combines two of these methods to make added hardware.