Compressor based 8×8 BIT vedic multiplier using reversible logic
G. Sree Lakshmi, DrKaleem Fatima, B. K. Madhavi · 2016
Reversible logic gates became very important and computing paradigm having its applications in low power CMOS technologies and Quantum computing [5]. Reversible logics are used to reduce the depth of the circuits [6]. This paper introduces a new architecture of 4:2 Compressor based Vedic 8×8 bit Multiplier using reversible logic and is compared with conventional multipliers using Reversible logic and it was observed that the parameters like Hardware Complexity, power and Delay are improved over other Reversible multipliers. The design is simulated, synthesized and power estimation was done using TSMC 180nm technology using Cadence Digital tools.