Reconfigurable future for HPC
Michaela Blott · 2016
Summary form only given. With Exascale systems on the horizon at the same time that conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy-efficiency, and cooling as first-class constraints concerns for scalable HPC. FPGAs can tailor the hardware to the application through customized datapaths and memory architectures. Thereby FPGAs can achieve much higher energy efficiencies compared to conventional CPU- and GPU-based solutions. This has stimulated interest in their exploitation within power-hungry data centers [1] with recent benchmarks showing that FPGA-based application acceleration can bring orders of magnitude improvement in regards to performance and performance per Watt compared to CPU/GPU counterparts [2,3,4]. The potential for FPGAs within HPC continues to be demonstrated by various individual research efforts [5,6,7,8] which span a broad range of applications, spanning from machine learning to graph traversal to genome sequencing. However, typically this work has been implemented through cumbersome, hardware-centric RTL design flows, the traditional FPGA development path, which is not really accessible to larger parts of the HPC community which are used to a different more abstract design environment and requires very different skill sets. Driven by this need, new software-centric design environments are emerging that can tremendously boost the productivity of designers and open up FPGA acceleration to the masses of software engineers. During this talk, we will present latest advances in software-centric design environments, such as Xilinx's new OpenCL based design tool [9], and elaborate on our ongoing efforts within the Xilinx research organization to benchmark and characterize a wide spectrum of applications with FPGAs, GPUs, Xeons and Xeon Phis.