Software defined Network-on-Chip for scalable CMPs
Alberto Scionti, Somnath Mazumdar, Antoni Portero · 2016
Moving from Petascale to Exascale computing necessitates optimizing the micro-architectural to increase the performance/power ratio of multicores (e.g., FLOPS/W). Future manycore processors will contain thousands of low-powered processing elements (kilo-core Chip Multi-Processors - CMPs) to support the execution of a large number of concurrent threads. While data-driven Program eXecution Models (PXMs) are gaining popularity due to the support they provide for thread communication, frequent data exchange among many concurrent threads puts stress on the underlying interconnect subsystem. This results in hotspots and high latency for data packet delivering. As a solution, we propose a scalable Software Defined Network-on-Chip (SDNoC) architecture for future manycore processors. Our design tries to merge the benefits of ring-based NoCs (i.e., performance, energy efficiency) with those brought by dynamic reconfiguration (i.e., adaptation, fault tolerance) while keeping the hard-wired topology (2D-mesh) fixed. To potentially accommodate different application and communication requirements, our interconnect allows mapping different types of topologies (virtual topologies). To allow the software layer to control and monitor the NoC subsystem, few customized instructions supporting a data-driven PXM are added to the core ISA. In experiments, we compared our lightweight reconfigurable architecture to a conventional 2D-mesh interconnection subsystem. Results show that our model allows savings of 39.4% of the chip area and up to 72.4% of the consumed power.