On Die Bit Error Rate Estimator for NAND Flash Memory
Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy · IEEE Transactions on Circuits & Systems II Express Briefs · 2016
In this brief, we propose a simple bit error rate (BER) estimator utilizing the parity check constraints of a low-density parity-check code-based error correction coding (ECC) scheme. The proposed estimator can be efficiently implemented on flash memory die with a very small area cost. We articulate applications in which flash memory controllers can take advantage of having the BER estimate before the ECC decoding scheme to significantly reduce programming errors and improve system performance in terms of latency and throughput.