Modeling a switch architecture with virtual output queues and virtual channels in HPC-systems simulators
Pedro Yébenes, German Maglione-Mathey, Jesús Escudero‐Sahuquillo, Pedro J. García, Francisco José Quiles · 2016
The high-performance switches used in the interconnection networks of HPC systems have evolved in the last years incorporating new features that were proposed decades ago as theoretical concepts but were then unfeasible due to technological constraints. One of these features are the Virtual Output Queues (VOQs) which can be included in current switch architectures. This approach consists in implementing at each input port as many queues as there are output ports in order to eliminate low-order Head-of-Line blocking. Besides VOQs, Virtual Channels (VCs) are usually implemented in current switch architectures. Both features can be jointly configured to improve switch performance. For that reason, new techniques and proposals exploit their advantages while they solve their drawbacks. Usually, the earliest evaluations of these new improvements are performed using network simulators. These tools allow network designers and manufactures to save time in the testing and development of new components. This paper focuses on the modeling of a switch architecture with VOQs and VCs and its implementation in HPC-systems simulators. We describe the basics of the pipelined switch architecture assumed for the model, i.e., the stages and operations applied to packets crossing it. We also detail the modeling of VOQs through several pseudo-code algorithms, ready to be adapted to any network simulator. Finally, we use an OMNeT++-based simulator for implementing and evaluating the model by means of several topologies, traffic scenarios and buffer organizations.