Coverage Driven Verification of IEEE P1500-compliant Embedded Core Test Infrastructures
Thanasis Oikonomou, Iraklis Diamantidis, Stylianos Diamantidis · 2005
Core-based design and reuse have been the key elements of efficient System-On-Chip (SoC) development. Testing of the embedded cores, however, introduces important challenges, such as core test reuse and interoperability at the SoC level, as well as the need for defining a common test infrastructure among cores from different suppliers. The IEEE 1500 Proposal for a Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores together with a Core Test Language. In this paper we justify the need to thoroughly verify the functionality of the complete testing hardware infrastructure in P1500-compliant SoCs. We present a coverage-driven verification approach based on an eVC architecture, which can be part of the overall SoC level validation strategy, being equally flexible and extensible to the IEEE P1500’s proposed hardware infrastructure. 1.