Runtime Reconfigurable Multi-Processor Architectures
Lomberto P. Jimenez · 2015
This thesis concentrated on the runtime reconfiguration of system-on-chip (SoC) cores to execute specific tasks. The premise was that if the cores could be reconfigured at runtime, their performance would improve when compared to general purpose cores. This thesis is comprised of two major components: the design of the system using the Verilog hardware description language (HDL), and the system’s implementation in a field-programmable gate array (FPGA) device. After implementing the read, write, and program commands, the Verilog simulations demonstrated that the system’s timing and the master-to-slave communication requirements were satisfied. For system implementation, a full image and various partial reconfigurable images were created. The feasibility of partial reconfiguration was demonstrated when specific FPGA partitions were reprogrammed at runtime. While the full image programming took 22 s, partial reconfiguration varied from 1 – 5 s based on the selected function. In addition to reduced programming times, the system benefited from having task-specific reconfigurable partitions.