Fault tuples: theory and applications
R. D. Blanton, K.N. Dwarakanath · 2004
The classical single stuck-line (SSL) fault model has been the most commonly used fault model in manufacturing test of digital circuit systems. However, as we push towards newer and more advanced technologies, the SSL fault model is proving to be inadequate due to the growing number of defect types going undetected by the tests generated for SSL faults. Although, several fault types like the bridging fault, transition fault, path delay fault, etc. have been introduced to alleviate the problem of inaccurate modeling of defect behavior, there seems to be no permanent solution in sight. No single fault model seems to be capable of modeling all existing and emerging misbehaviors. The problem of manufacturing reliable and working digital integrated circuits is further compounded by the non-availability of test analysis tools to perform manufacturing test analysis of new defect types. An ideal solution to the above mentioned problems is a fault modeling mechanism that is general enough to allow description of the behavior of any type of defect. In this dissertation, we examine the capabilities of a novel fault representation mechanism based on fault tuples as a generalized fault modeling mechanism. A fault tuple is a 3-element tuple f = (l, v, t), where v is the value desired on signal line l during the time-frame described by element t. The syntax and semantics of fault tuples are described in this dissertation. We show how combinations of fault tuples are used to represent the logic-level behavior of defects. The implementation issues of test analysis tools based on generalized fault modeling mechanism are addressed by describing the implementation details of FATSIM, a fault simulation system based on fault tuples. FATSIM is an event-driven, gate-level, synchronous sequential fault simulator capable of simulating the properties of fault tuple based macrofaults. The manufacturing test tasks of (a) fault grading, (b) generating fault dictionaries, and (c) fault ordering for test generation are used to demonstrate the capabilities of fault tuples and test analysis tools based on fault tuples.