High Speed and Area Efficient Discrete Wavelet Transform Using Vedic Multiplier
Satyendra Tripathi, Ashutosh Kumar Singh · 2015
With the emergence of technology in the field of communication and VLSI, also growing demand of high speed processing and low area design. The multipliers a key factor in arithmetic operation and digital signal processing algorithm. Multiplier forms an integral part of processor design. Multiplier takes long time for execution so that there is a need of fast multiplier save the execution. For image and digital signal processing require multiplication, so need to design a multiplier for wavelet transform which contain low area and provide a high speed. This paper delineates the multiplication using Vedic multiplication technique. These design reduced hard complexity, throughput rate and different input/output data format to match different application needs. These techniques are designed implementation on Spartan 3 FPGA. We've synthesized the planned styles and therefore the existing style mistreatment synopsis tools.