High-speed and low power dissipation architecture for higher-order FIR filters with very small latency
Yoshitaka Tsunekawa, Takeshi Nozaki, Mamoru Miura · IEEJ Transactions on Electronics Information and Systems · 1998
This paper presents high-speed and low power dissipation architecture for higher-order FIR filters with very small latency. To minimize power dissipation and latency, the distributed arithmetic, of which processing time depends on only word length, is applied to this architecture. The basic structure method of function Φ using ROMs has been proposed so far. However this method for function Φ requires very high power dissipation and wide area in VLSI chip, because of using ROM of much larger capacity for higher filter order. So, we propose a new implementation approach of the function Φ using logic gates. We also reveal a new method of lower power dissipation, by making use of a perfect linear phase characteristic of FIR filters. As a result, by using 0.8μm CMOS technology we show that a 120-tap FIR digital filter can be realized with high sampling rate of about 2.74MHz and the small latency of 572ns. These values are almost independent of filter order. Moreover this processor is implemented with power of 1.61W, which can decrease power dissipation to about 13.9% as compared with conventional implementation using multipliers.