Preliminary Evaluations for Hybrid Memory Cube with Gather Functions Using FPGA
Boonyasitpichai Nuttapon · 2012
In Exa FLOPS scale machines, Byte/FLOP ratio which decides performance of many focused applications must be degraded severely from now. Therefore, the solution for the problem from the standpoint of performance and power is desired. In this report, the authors propose Hybrid Memory Cube (HMC) with gather functions as a solution for it. It is preliminary evaluated using FPGA. We got results which support the validity of our design policy in the design parameter space for 3D stacking. We confirmed the acceleration ratio from 11 to 13 in the indirect array references can be obtained by implementing gather functions in an HMC. We confirmed the needed capacity of logic gates of the controller is enough with the middle-class FPGA of 2 generation older than that of the newest generation. 1. はじめに