Address Counter / Generators for Low Power Memory BIST
Sukhleen Bindra Narang, Arun Khosla · 2011
In today’s Integrated Circuits (IC’s) designs Built-in Self Test (BIST) is becoming important for the memory which is the most necessary part of the System on Chip. The March algorithm has been widely used to test memory core of System on chip (SOC). LFSRs and counters are mainly used to generate the memory addresses, which can be serially applied to the memory cores under test. I n this paper Address counters and Data generators (i.e. parts of the MBIST) are designed. These implemented in Hardware Description Language (HDL), and the area and power analyzed for each case . From the analyzed results the low power LFSRs and counters can be identify for the low power memory BIST design.