Real World FPGA Design With Verilog with CDROM
Ken Coffman · Prentice-Hall, Inc eBooks · 1999
From the Book: PREFACE: Preface: Digital Design in the Real World The world of digital design is changing quickly. At a breathtaking rate, devices are becoming faster, smaller, and denser. Ten years ago the mainstream digital designer was manipulating a few thousand gates using schematics with an occasional ABEL-HDL module tossed into the mix. Now we have programmable devices with a million gates in tiny packages. On the horizon, we see devices with many more millions of gates. It is not practical for the mainstream designer to create systems on chips with schematics (how would you like to deal with a 1,000-page schematic?), so Hardware Description Languages like VHDL and Verilog have come into their own. In spite of strong opinions on both sides of the fence (including my own), the current designscape is bilingual-multilingual if you include the work of those translating C code into hardware and the work of others on more advanced and hybrid languages. My own opinion of the fundamental reason for Verilog's staying power is that Verilog had a very large head start in the number of engineers who knew Verilog before VHDL really got out of the blocks, and Verilog is easier to learn than VHDL. Thus, the established designers already knew Verilog and had no reason to learn VHDL, and the new designers could pick it up easier than they could pick up VHDL. John Sanguinetti C2 Design Automation I always thought that VHDL was the bloated/bureaucratic/design-by-committee deal, and Verilog was the KISS/lean-and-mean/hippy/West Coast approach, and that the usual rules-of-engagement required us to perpetuate and widen the riftbetweenthem :) Jonathan Bromley School of Engineering Oxford Brookes University SURVIVAL SKILLS Regardless of personal opinions, the practical designer will make sure that both VHDL and Verilog skills are present on his or her resume. The current half-life of engineering information is about four years and gets shorter every day. This means that half of what you know today will be obsolete in four years. In order to survive, we weary designers have to do two things: Master the parts of our skill that are timeless. This includes physics (the analog aspects of digital design, transmission-line theory, conservation of energy, antenna theory, and power management) and design concepts like synchronization, metastability, and propagation delay. Keep up with the changing technology. Take advantage of free seminars, try to read some of the tidal wave of trade magazines that pile up every month, buy as many books as your Significant Other will tolerate, and pay close attention when smart people are speaking. 80% of all embedded systems are delivered late. Jack Ganssle The Ganssle Group The world of digital design is deeply divided. The elite 10%, the ASIC designers, use hardware and software tools that cost hundreds of thousands of dollars a year to maintain. They earn their living creating specialized high-volume designs. If the FPGA designer uses 50K gates, the ASIC designer uses 500K gates. If the FPGA designer is accustomed to four nanoseconds of delay through a primitive, the ASIC designer is accustomed to delays of less than a nanosecond. The ASIC designer is very careful, methodical, and does extensive planning. Errors can cost hundreds of thousands of dollars in silicon turns and schedule delays. The ASIC designer simulates, simulates, and then simulates some more. By contrast, we FPGA designers are sloppy and impatient. There is little or no cost to experiment, so we program a part and try it. We use tools that are cheap or free on Windows-based PCs. By comparison to ASIC designers, we are a brutish and undisciplined mob, an unruly 90%. I have written this book for those who would like to join me in this mob. There's also the human elementstressto the reprogrammability equation. ASICs aren't reprogrammable; the foundry casts their functionality into silicon. Making the final decision to commit a design to an ASIC can be extremely stressful for the entire design team. Once it makes the final decision, the team can't go back without incurring lots more NRE and lots more time. Erring at this stage, thus, is definitely a Career-Limiting Move (CLM). FPGAs, on the other hand, offer engineers a greater comfort zone midway through the project, giving them the ability to go back and revise a design without paying the NRE and time penalties. Reprogrammability alone may well be responsible for much of the success of the FPGA marketplace in the last decade. Rockland K. Awalt Making the ASIC/FPGA Decision Integrated System Design, July 1999 Reprinted by permission This is an FPGA synthesis book. It will not make the reader into an ASIC designer, though it does address issues associated with converting an FPGA design to an ASIC. This book is for the newbie FPGA designer who wants a quick and dirty guide to creating FPGA designs that actually stand a chance of surviving in the Real World. The CD-ROM includes the evaluation version of the Silos III simulator. This software includes a project/file manager, waveform viewer, and full-featured Verilog support. The CD-ROM also includes the demonstration version of David Murray's excellent Prism Editor. This editor includes an automatic commenting/uncommenting feature, smart indentation, color coded Verilog keywords, printing of keywords in bold, column editing, and handling of Verilog code templates. A special price of USD $40.00 was negotiated for purchaser's of this book for those who choose to register the Prism Editor. Also on the CD-ROM is a fully-functional evaluation version of Emath-Pro for Windows, an electronics formula tool with over 300 useful formulas in 19 categories. I worked hard on this book, but it is not perfect. If you find an error or want to argue about some of the points that are arguable (of which there are many), I look forward to hearing from you. Ken Coffman Mount Vernon, Washington [email protected]