A semi-systolic VLSI architecture for majority-logic error-correction decoding
Habib Krit · 1992
This thesis presents a semi-systolic architecture for implementing Majority-Logic Decoding of cyclic and convolutional codes. The architecture was first described by Karplus for a variant of Tanner's Algorithm B called Algorithm B-lite. The error correction capability of this algorithm is not tightly bound and accurate guidelines for picking good codes are lacking. In this thesis, Algorithm B-lite is proved to be identical to Approximate A Posteriori Probabilities Threshold Decoding. The semi-systolic architecture is compared to the traditional implementation of Threshold Decoding. Codes for which the new architecture applies are described. Several modifications are proposed to reduce the hardware complexity of the semi-systolic architecture. The effect of each modification on performance is determined by simulation. The results of this investigation were used to construct a prototype chip that decodes a 73-bit Difference Set Code. This 4600$\mu$m-by-6800$\mu$m chip should achieve 25 MHz decoding in 2$\mu$m n-well CMOS.