Built-in test design for the efficient testing of vlsi circuits
Robert Molyneaux, Alexander Albicki · 1991
This dissertation addresses the issues involved in incorporating testability into an integrated circuit design, with the physical activity taking place at the register transfer stage of circuit development. The modules within a register transfer diagram are partitioned into entities called Test Units which display properties that are very desirable from a testing perspective. A set of boundary modules is defined for a given Test Unit, and any functionally feasible vector may be induced at the input to any module within the Test Unit by the application of a single test vector at the inputs to the boundary modules. The desirable property of the Test Unit is evident in the statement that to induce an input vector at a module within a Test Unit requires, not a sequence of inputs, but only a single input at the boundary modules. The Test Unit may therefore be regarded informally as a combinational circuit with delay. This relieves fault simulation and test pattern generation programs from the computationally more complex task of analyzing sequential structures. Furthermore, this independence from specific text sequences renders Test Units ideal targets for on-chip test pattern generators, where specific test sequences are more difficult to produce than random or pseudo-random sequences. An example of the usefulness of Test Unit for the implementation of the BILBO self-test technique is given. Self-test techniques require operational procedures to be derived in order that the on-chip Test Resources be activated in an appropriate and efficient order. The derivation of procedures for testing requires a scheduling of the tests that must be performed. The tests are grouped into test sessions in such a way as to minimize the total time required to perform all of the tests. All of the tests within a session are executed simultaneously; therefore no two tests within a session can have conflicting requirements for the operational mode of a given circuit. The solution to the test scheduling problem is exponential and, as formulated in this dissertation, is infeasible for problem instances with more than 9 or 10 tests to be scheduled. Approximate solutions are susceptible to large deviations from the optimal solution. Therefore, a hybrid solution to this scheduling problem is presented that provides a good solution while also facilitating the determination of an upper bound on the deviation of the solution from the optimal.