An efficient prime factor memory-based FFT processor for LTE systems
Xia Kaifeng, Bin Wu, Xiaoping Zhou, Tao Xiong · 2016
This paper presents an efficient memory-based fast Fourier transform processor including 35 different working sizes for LTE systems. A factorization method named high-radix-small-butterfly combined with a conflict-free address scheme for 2p3q5rpoint memory-based FFT processor is proposed. The processor can not only provide conflict-free concurrent data access from different memory banks but also continuous-flow working mode. Moreover, we exploit prime factor algorithm to decrease the multiplications and twiddle factor storage. In addition, a unified Winograd Fourier transform algorithm butterfly core was designed for the small 2, 3, 4, 5-point DFTs. The FFT processor was implemented in a SMIC 55nm CMOS process with core area 1.063mm2. The chip consumes 40 8mW at 122.88MHz operating frequency with 1.08V voltage supply.