Using Existing Reconfigurable Logic in 3D Die Stacks for Test
Fanchen Zhang, Sun Yi, Xi Zhong Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Ruth Iris Bahar, Alfred L. Crouch, John Potter · 2016
We propose an architecture for an FPGA-based tester for a 3D stacked IC. Our design exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns at a high bandwidth, reducing the FPGA resources required and often reducing scan shift toggling. The proposed approach and its advantages can generally also be applied to 2.5D multi-die circuits containing FPGAs.