AES Implementation on Virtex-6 FPGA for Enhanced performance using pipelining and partial reconfiguration techniques
K. Navatha, J.Tarun Kumar, Pratik Ganguly · IOSR Journal of VLSI and Signal processing · 2016
Implementation of Encryption Standard system (AES) by efficient code optimization and partial reconfigurationtechniques has been presented in this paper.128 bit block size and cipher key have been used for this AES implementation.Rijndael algorithm which is also referred as AES is mainly used for ensuring transmission channels security.Xilinx design tool 13.3 and Xilinx project navigator tools are used for synthesis and simulation purpose.For coding of the design, VHDL language has been used.Pipelined design has been implemented on Virtex 6 FPGA device and a throughput of 49.3Gbits/s is achieved with the frequency of 384.793MHz.