A testbench research based on UVM for ABCStar
L. X. Cheng, Francis Anghinolfi, Ke Wang, Hong-Bo Zhu, Wei-Guo Lu, Zhen-An Liu · 2016
As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constructed testbench based on Universal Verification Methodology(UVM) research for ATLAS Phase-II upgrade silicon strip detector front-end readout chip.