Soft-error resilient Network-on-Chip for safety-critical applications
Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah · 2016
Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the packet switched NoC paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors have severe consequences on system performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D Network-on-Chip (SER-3DR-NoC) architecture and design targeted for safety-critical embedded applications. Evaluation results show that the SER-3DR-NoC is able to achieve a high level of transient error protection with a little performance degradation and a small power overhead.