An efficient sub-sample interpolator hardware for VP9-10 standards
Guilherme Paim, Wagner Penny, Jones Göebel, Vladimir Afonso, Altamiro Susin, Marcelo Porto, Bruno Zatt, Luciano Volcan Agostini · 2016
This paper presents a hardware design for the sub-sample interpolator used in FME (Fractional Motion Estimation) and MC (Motion Compensation) stages according to the VP9 and VP10 video-coding standards. The proposed architecture is able to save hardware resources through an optimized-filter organization whereas reaching high-throughput and low-power dissipation. The hardware design was described in Verilog and synthesized for ASIC technology. The synthesis results were generated for 45nm Nangate standard cells and demonstrate that the developed architecture is able to process 2160p@60fps videos with a power dissipation of 2.34mW focusing on a VP9-10 decoder.