A RISC processor for high-speed execution of genetic algorithms
Shinya Koizumi, Shin’ichi Wakabayashi, Tetsushi Koide, Kazunari Fujiwara, Norimichi Imura · 2001
This paper proposes a new RISC processor for high speed execution of genetic algorithms (GAs). The proposed RISC processor is designed based on the DLX instruction set, and a set of new instructions, which are effective to highspeed execution of GAs, are added. Since a GA is implemented as software on the proposed processor, any type of GA can be realized. Using the instruction set of the proposed processor, more than 90 % reduction of the number of clocks to execute GA operators such as 2-point crossover can be achieved. The processor has been designed with the Verilog Hardware Description Language to be implemented as a VLSI chip with a 0.35µm standard cell technology.