An Integrated Framework for Application Engine Synthesis and Verification from High Level C Algorithms
Shail Aditya, Vinod Kathail · 2008
The increasing SoC complexity and a relentless pressure to reduce time- to-market have left the hardware and system designers with an enormous design challenge. The bulk of the effort in designing an SoC is focused on the design of product-defining application engines such as video codecs and wireless modems. Automatic synthesis of such application engines from a high level algorithmic description can significantly reduce both design time and design cost. This chap- ter reviews high level requirements for such a system and then describes the PICO (Program-In, Chip-Out) system, which provides an integrated framework for the synthesis and verification of application engines from high level C algorithms. PICO's novel approach relies on aggressive compiler technology, a parallel exe- cution model based on Kahn process networks, and a carefully designed hardware architecture template that is cost-efficient, provides high performance, and is sen- sitive to circuit level and system level design constraints. PICO addresses the complete hardware design flow including architecture exploration, RTL design, RTL verification, system validation and system integration. For a large class of modern embedded applications, PICO's approach has been shown to yield extremely com- petitive designs at a fraction of the resources used traditionally thereby closing the proverbial design productivity gap.