An optimized implementation of logarithm hardware generator for digital signal processing
Van-Thuan Sai, Van‐Phuc Hoang · 2016
This paper presents an optimized hardware approximation of logarithm function for digital signal processing systems. The proposed method combines the multi-segment linear approximation with a small look-up table and an optimization algorithm to trade-off the computation speed with the hardware complexity. As a result, an efficient logarithm generator with simple structure and high computation speed is presented. The implementation results are also discussed.